Image processing apparatus and method, and recorded medium

ABSTRACT

A picture processing apparatus for processing picture signals of different formats. A memory stores input picture signals. A read-out section reads the picture signals stored in the memory in terms of a preset number of the picture signals as a unit. An interpolation section interpolates picture signals for a preset position by executing preset calculations on the plural picture signals read out. For picture signals of an HD format, the picture signals are simultaneously read out in terms of the four pixels as a unit to execute four-point interpolation processing. Whilst for picture signals of an SD format, after a conversion to a 960.times.720 frame picture by applying field/frame conversion and doubling the number of the pixels in the vertical direction, the picture signals are stored in the memory. The operating frequency and the number of times of operations of the read-out section and the interpolation section are changed to values as large as four times those. Thus, the picture signals of the SD format are simultaneously read out four times in terms of the four pixels as a unit to execute the 16-point interpolation processing.

TECHNICAL FIELD

This invention relates to a picture processing method and apparatus andto a recording medium. For example, it relates to a picture processingmethod and apparatus conveniently used for arbitrarily changing theshape of a picture and displaying the so changed picture, and to arecording medium.

BACKGROUND ART

The advent of digital storage contributes significantly to the technicalprogress in the production technique of television programs. The DRAM,among different types of the digital storage, is gradually increasing inits storage capacity so that one scanning line, one field picture, oneframe picture and even a sequence of plural pictures can be storedtherein. The digital storage is economically practicable even inconsideration of its production cost, circuit scale or powerconsumption. Among the instances of application of the digital storage,such as DRAM, there are so-called DME (digital multi-effects) used whenmodifying the picture to an optional shape or when moving the picturesuch as at the time of creation of television programs.

Meanwhile, when e.g., the conventional DME executes processing ofinterpolation of picture signals of the conventional HD (highdefinition) format, so-called four-point interpolation, which consistsin calculating picture signals of a position for interpolation usingpicture signals corresponding to four pixels lying around the positionfor interpolation, is used. If the conventional DME execute processingof the interpolation on picture signals of the SD (standard definition)format, the processing of so-called 16-point interpolation is used, inwhich, after field/frame conversion, the number of horizontal scanninglines is doubled, and picture signals at the position of interpolationare calculated using picture signals corresponding to 16 pixels lying inthe vicinity of the position of interpolation. If now the four-pointinterpolation is applied to picture signals of the SD format, thepicture signals resulting from the interpolation are lower in qualitythan those obtained on 16-point interpolation. It is therefore desirableif, in implementing DME capable of processing picture signals of the HDformat and those of the SD format, the four-point interpolation and the16-point interpolation can be executed for picture signals of the SDformat and those of the HD format, respectively. However, there lackssuch DME in the current technical level.

Also, in the DME, it is practiced to interpolate picture signals at acertain position using picture signals of plural signals lying aroundthe position, for example, four pixels lying at upper, lower, left andright positions. However, if the position desired for interpolation isnear a picture edge, it may be an occurrence that no sufficient numberof neighboring pixels is available. In such case, processing differentfrom the usual interpolation is needed. That is, there is the necessityof verifying whether or not the processing of usual interpolation isapplicable to the particular position for interpolation. Consequently, adedicated circuit for making the decision in this respect is needed.

In the conventional DME, it is also practiced to interpolate picturesignals of a preset position with picture signals of pixels lying in thevicinity of the position. However, since the picture signals input toe.g., the DME are of the 4:2:2 (Y/U/Y) format, in which the positions ofthe chroma signals U, V associated with luminance signals Y aregeometrically offset, there is raised a problem that a memory cannot beefficiently utilized. There is also an additional problem that, sincethe luminance signals Y and the chroma signals U, V are different in thespatial frequencies from each other, processing pertinent to color, suchas colored spotlight effect or trailing effects accompanied with colorchanges, cannot be performed.

In the conventional DME, directed to the processing of the SD formatpicture signals, a field memory is used for changing the scanningdirection from the horizontal direction to the vertical direction.However, if it is considered to process the picture signals of the HD(high definition) format, higher in resolution higher than the picturesignals of the SD format, a larger storage capacity and a higherread-write speed, are required, thus raising a problem that theconventional field memory cannot be used.

On the other hand, if a general-purpose memory is usable in producinge.g., the DME, low cost can be achieved. However, in view of thelimitations imposed on the sorts of the bit widths of thegeneral-purpose memory, the bit width of input picture signals needs tobe matched to the bit width of the general-purpose memory.

DISCLOSURE OF THE INVENTION

In view of the above-described status of the art, it is an object of thepresent invention to provide a picture processing method and apparatus,and a recording medium, according to which 4-point interpolation can beapplied to picture signals of the HD format, whilst 16-pointinterpolation processing can be applied to picture signals of the SDformat.

It is another object of the present invention to provide picture aprocessing method and apparatus, and a recording medium, according towhich, in interpolating picture signals, the same processing ofinterpolation can be applied regardless of interpolating positions.

It is still another object of the present invention to provide a pictureprocessing method and apparatus, and a recording medium, according towhich, by converting the 4:2:2 (Y/U/V) picture signals into 4:4:4(Y/U/V) picture signals, it becomes possible to make efficientutilization of the memory as well as to effect processing pertinent tocolor operations.

It is still another object of the present invention to provide a pictureprocessing method and apparatus, and a recording medium, according towhich the scanning direction can be changed by exploiting an SDRAM(Synchronous Dynamic Random Access Memory), which features bursttransfer, in place of the routinely used field memory.

It is yet another object of the present invention to provide a pictureprocessing method and apparatus, and a recording medium, according towhich the information volume taken up by the chroma signals U, V in thepicture signals of the 40-bit width of the 4:4:4:4 (Y/U/V/K) format maybe curtailed to reduce the cost by conversion to picture signals of36-bit width to enable the use of the general-purpose memory of 36-bitwidth.

A picture processing apparatus for processing picture signals ofdifferent formats, according to the present invention, includes storagemeans for storing input picture signals in a memory, read-out means forsimultaneously reading out the picture signals stored in the memory interms of a preset number of the picture signals as a unit, interpolationmeans for interpolating picture signals for a preset position byexecuting preset calculations on the plural picture signals read out bythe readout means from the memory, and control means for controlling theoperating frequency and the number of times of operations of the readoutmeans and the interpolation means in keeping with the formats of theinput picture signals.

A picture processing method for processing picture signals of differentformats, according to the present invention includes a storage step ofstoring input picture signals in a memory, a read-out step ofsimultaneously reading out the picture signals stored in the memory interms of a preset number of the picture signals as a unit, aninterpolation step of interpolating picture signals for a presetposition by executing preset calculations on the plural picture signalsread out in the readout step from the memory, and a control step ofcontrolling the operating frequency and the number of times ofoperations of the readout step and the interpolation step in keepingwith the formats of the input picture signals.

A recording medium according to the present invention includes acomputer-readable program for picture processing, recorded thereon, inwhich the program includes a storage step of storing input picturesignals in a memory, a read-out step of simultaneously reading out thepicture signals stored in the memory in terms of a preset number of thepicture signals as a unit, an interpolation step of interpolatingpicture signals for a preset position by executing preset calculationson the plural picture signals read out in the readout step from thememory, and a control step of controlling the operating frequency andthe number of times of operations of the readout step and theinterpolation step in keeping with the formats of the input picturesignals.

A picture processing apparatus for interpolating picture signalsaccording to the present invention includes storage means for storingthe picture signals corresponding to input pixels in a memory,generating means for setting an imaginary area around a picture formedby the picture signals for generating the picture signals associatedwith the imaginary area, storage means for storing the picture signalsassociated with the imaginary area, generated by the generating means,readout means for reading out the plural picture signals associated withplural pixels lying in the vicinity of a preset position, andinterpolation means for interpolating the picture signals associatedwith the preset position using plural picture signals associated withthe plural pixels read out by the readout means.

A picture processing method for interpolating picture signals accordingto the present invention includes a storage step of storing the picturesignals corresponding to input pixels in a memory, a generating step ofsetting an imaginary area around a picture formed by the picture signalsfor generating the picture signals associated with the imaginary area, astorage step of storing the picture signals associated with theimaginary area, generated by the generating step, a readout step ofreading out the plural picture signals associated with plural pixelslying in the vicinity of a preset position, and an interpolation step ofinterpolating the picture signals associated with the preset positionusing plural picture signals associated with the plural pixels read outby the readout step.

A recording medium according to the present invention includes acomputer-readable program for picture processing, recorded thereon, inwhich the program includes a storage step of storing the picture signalscorresponding to input pixels in a memory, a generating step of settingan imaginary area around a picture formed by the picture signals forgenerating the picture signals associated with the imaginary area, astorage step of storing the picture signals associated with theimaginary area, generated by the generating step, a readout step ofreading out the plural picture signals associated with plural pixelslying in the vicinity of a preset position, and an interpolation step ofinterpolating the picture signals associated with the preset positionusing plural picture signals associated with the plural pixels read outby the readout step.

A picture processing apparatus for interpolating picture signalsincluding at least luminance signals and chroma signals, according tothe present invention, includes separating means for separating thechroma signals from the picture signals corresponding to sequentiallyinput pixels, interpolation means for interpolating chroma signalsassociated with a preset position using a plurality of consecutivechroma signals, as separated by the separating means, and outputtingmeans for outputting the chroma signals, interpolated by theinterpolation means, simultaneously with corresponding luminancesignals.

A picture processing method for interpolating picture signals accordingto the present invention includes at least luminance signals and chromasignals, in which the method includes a separating step of separatingthe chroma signals from the picture signals corresponding tosequentially input pixels, an interpolation step of interpolating chromasignals associated with a preset position using a plurality ofconsecutive chroma signals, as separated by the separating step, and anoutputting step of outputting the chroma signals, interpolated by theinterpolation step, simultaneously with corresponding luminance signals.

A recording medium includes a computer-readable program for pictureprocessing, recorded thereon, in which the program interpolates picturesignals at least including luminance signals and chroma signals, andincludes a separating step of separating the chroma signals from thepicture signals corresponding to sequentially input pixels, aninterpolation step of interpolating chroma signals associated with apreset position using a plurality of consecutive chroma signals, asseparated by the separating step, and an outputting step of outputtingthe chroma signals, interpolated by the interpolation step,simultaneously with corresponding luminance signals.

A picture processing apparatus for converting the scanning direction forpicture signals according to the present invention includes writingmeans for alternately writing the picture signals, input in thehorizontal scanning sequence, in different ones of a plurality of banksof a first information recording medium, from one preset unit volume toanother, readout/writing means for alternately reading out the picturesignals every preset unit volume, for writing the information signals ina second information recording medium, and output control means foroutputting the picture signals every preset unit volume from the secondinformation recording medium in accordance with the writing sequence.

A picture processing method for converting the scanning direction forpicture signals according to the present invention includes a writingstep of alternately writing the picture signals, input in the horizontalscanning sequence, in different ones of a plurality of banks of a firstinformation recording medium, from one preset unit volume of the picturesignals to another, a readout/writing step of alternately reading outthe picture signals every preset unit volume of the picture signals, forwriting the information signals in a second information recordingmedium, and an output control step of outputting the picture signalsevery preset unit volume of the picture signals from the secondinformation recording medium in accordance with the writing sequence.

A recording medium includes a computer-readable program for pictureprocessing, recorded thereon, the program causing the scanning directionof picture signals to be changed, in which the program includes awriting step of alternately writing the picture signals, input in thehorizontal scanning sequence, in different ones of a plurality of banksof a first information recording medium, from one preset unit volume ofthe picture signals to another, a readout/writing step of alternatelyreading out the picture signals every preset unit volume of the inputpicture signals, for writing the information signals in a secondinformation recording medium, and an output control step of outputtingthe picture signals every preset unit volume of the input picturesignals from the second information recording medium in accordance withthe writing sequence.

A picture processing apparatus for changing a bit width of picturesignals according to the present invention includes conversion means forreducing the bit width of chroma signals of input picture signals tochange the bit width of the picture signals, and storage means forstoring the picture signals, converted in bit width by the conversionmeans to a preset bit width, in a memory.

A picture processing method for changing a bit width of picture signals,according to the present invention, includes a conversion step ofreducing the bit width of chroma signals of input picture signals tochange the bit width of the picture signals, and a storage step ofstoring the picture signals, converted in bit width in the conversionstep to a preset bit width, in a memory.

A recording medium according to the present invention includes acomputer-readable program for picture processing, recorded thereon, theprogram causing the bit width of picture signals to be changed, in whichthe program includes a conversion step of reducing the bit width ofchroma signals of input picture signals to change the bit width of thepicture signals, and a storage step of storing the picture signals,converted in the bit width in the conversion step to a preset bit width,in a memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an exemplary structure of a picturesynthesis apparatus embodying the present invention.

FIG. 2 is a block diagram showing an exemplary structure of DME3.

FIGS. 3A to 3C illustrate the concept of the processing forinterpolating the chroma signals U, V in an H filter 14.

FIG. 4 is a block diagram showing an exemplary structure of a portionconcerning the processing of interpolating the chroma signals U, V inthe H-filter 14.

FIG. 5 is a block diagram showing an exemplary structure of a 4-pointinterpolation circuit 40 of FIG. 4.

FIG. 6 is a block diagram showing an exemplary structure of a scanconverter 15.

FIG. 7 grossly shows the progress with time of the processing ofchanging the scanning direction of the scan converter 15 to aperpendicular direction on the field basis.

FIGS. 8A, 8B schematically show the relationship between SDRAMs 64-1,64-2 burst-transferring picture signals stored on the field basis in thesequence of vertical scanning and an SRAM 65 caching theburst-transferred picture signals.

FIG. 9 shows an exemplary timing of continuous accessing to two sorts ofbanks of the SDRAM 64.

FIG. 10 shows continuous accessing (writing) to the SDRAM 64.

FIG. 11 illustrates continuous accessing (readout) to the SDRAM 64.

FIG. 12 shows exemplary two-dimensional address allocation in 2-bank4-word burst of picture signals of the HD format (1080ix1920) for theSDRAM 64.

FIG. 13 illustrates a counter mechanism for generating write addressesfor the SDRAM 64.

FIG. 14 shows the continuous readout sequence from the SDRAM 64.

FIG. 15 illustrates a counter mechanism for generating read addressesfor the SDRAM 64.

FIG. 16 shows the concept of using a memory forming the SRAM 65 as aring.

FIGS. 17A to 17C show the concept of using four memories forming theSRAM 65 as a four-fold ring.

FIG. 18 illustrates the processing of converting picture signals(Y/U/V/K) into 36-bit width signals by a converter 67 curtailing thevalues of chroma signals U, V to 8 bits.

FIG. 19 is a block diagram showing n illustrative structure of a buffer20.

FIG. 20 is a block diagram showing an illustrative structure of unit U0of the buffer 20.

FIGS. 21A and 21B show allocation to units U0 to L1 of HD format picturesignals input from the scan converter 15.

FIG. 22 shows a coordinate system of read-out addresses set in thebuffer 20.

FIG. 23 shows the state of the writing of even-field picture signals ina data area of the buffer 20.

FIG. 24 shows positions of four pixels used for four-point interpolationprocessing.

FIG. 25 shows an instance where there lack four pixels used forfour-point interpolation processing.

FIG. 26 shows an ex-area data band provided in an effective access areaof the buffer 20.

FIG. 27 shows a state in which even-field picture signals are written ina data area of a buffer 20, with an ex-area data band being settherearound.

FIG. 28 illustrates the state in which 4-point interpolation becomespossible by the ex-area data band being set in the buffer 20.

FIG. 29A, 29B illustrate the relationship between a screen address and aread address.

FIG. 30 illustrates super-interpolation by an address generator 21.

FIG. 31 illustrates processing timing of super-interpolation.

FIG. 32 is a block diagram showing an illustrative structure of theaddress generator 21.

FIG. 33 is a block diagram showing an illustrative structure of asuper-interpolation block 93.

FIG. 34 shows function values X(0, 0) to Z(1919, 539) held byREG_V_START_XL register 101-X to REG_V_END_ZR register 106-Z.

FIG. 35 shows the relationship between registers enclosed in a mixercoefficient block 92 and mixer coefficients held therein.

FIG. 36 shows the originating point and an outputting destination of thefunction values for mixers 111-X to 111-Z.

FIG. 37 shows the state of a block for interpolating the function valuesX(H, V) in association with FIG. 36.

FIG. 38 shows the originating point and an outputting destination of thefunction values for mixers 111-X to 111-Z.

FIG. 39 shows the state of a block for interpolating the function valuesX(H, V) in association with FIG. 38.

FIG. 40 shows the originating point and an outputting destination of thefunction values for mixers 111-X to 111-Z.

FIG. 41 shows the state of a block for interpolating the function valuesX(H, V) in association with FIG. 40.

FIG. 42 is a block diagram showing an illustrative structure of aninterpolation circuit 42.

FIG. 43 is a block diagram showing an illustrative structure of avertical proportional distribution circuit 121.

FIG. 44 is a block diagram showing an illustrative structure of ahorizontal proportional distribution circuit 123.

FIG. 45 shows values of interpolation coefficients C₀ to C₇ used in16-point interpolation processing.

FIG. 46 illustrates four-point interpolation processing for picturesignals of the HD format.

FIG. 47 illustrates field/frame conversion for the picture signals ofthe SD format by a converter 67 of the scan converter 15.

FIG. 48 shows allocation to units U0 to L1 of field/frame convertedpicture signals of the SD format input from the scan converter 15.

FIG. 49 illustrates 16-point interpolation processing for picturesignals of the SD format.

FIG. 50 illustrates the operation of vertical proportional distributioncircuits 121, 122 in 16-point interpolation processing.

FIG. 51 illustrates the operation of a horizontal proportionaldistribution circuit 123 in 16-point interpolation processing.

FIG. 52 illustrates the readout timing of picture signals in 16-pointinterpolation processing.

FIG. 53 illustrates the operating timing of the vertical proportionaldistribution circuits 121, 122 in the 16-point interpolation processing.

FIG. 54 illustrates the operating timing of the horizontal proportionaldistribution circuit 123 in the 16-point interpolation processing.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to the drawings, the picture processing method and apparatusaccording to the present invention are explained in detail. FIG. 1 showsa block diagram showing the structure of a picture synthesis apparatusembodying the present invention. This picture synthesis apparatus isused in, for example, creating television broadcast programs, andsynthesizes pictures of input video signals A and B, already subjectedto digital picture processing, such as transformation or translation, tooutput the resulting synthesized picture.

The picture synthesis apparatus is made up of an arm lever 1, detectingthe user's operation to output corresponding operating signals to acontrol circuit 2, which control circuit 2 controls a drive 5 to cause acontrol program stored in a magnetic disc 6, inclusive of a floppy disc,an optical disc 7, inclusive of a CD-ROM (Compact Disc-Read OnlyMemory), a DVD (Digital Versatile Disc) and a magneto-optical disc 8,inclusive of an MD (Mini-Disc), to be read out to control the entirepicture synthesizing apparatus based e.g., on the so read out controlprogram and on the operating signals from an arm lever 1, and a DME 3for applying digital picture processing to the input video signals A tooutput the resulting signals to a synthesis circuit 4. The synthesiscircuit 4 superposes a picture of the input video signals A, subjectedto the digital picture processing, to the picture of the input videosignals B, to output the resulting signal to the downstream sidecircuitry.

The operation of a picture synthesis apparatus is now explained. The DME3 applies digital picture processing, associated with the user'soperations on the arm lever 1, to the picture of input video signals A.The synthesis circuit 4 then superimposes the resulting signals on apicture of input video signals B to output the resulting picture.

FIG. 2 shows a block diagram showing a specified structure of the DME 3. The input video signals A, fed to the DME 3, are assumed to be picturesignals of a 30 bit width of the 4:2:2:4 (Y/U/V/K) HD format (e.g.,1080i×1920), that is picture signals made up by luminance signals Y of a10-bit width, chroma signals U, V, each of a 5-bit width and a keysignal K of a 10-bit width. The input video signals A may be picturesignals of the SD (Standard Definition) format (e.g., 480i×720), orpicture signals of any other suitable format, in addition to beingpicture signals of the HD (High Definition) format. Meanwhile, in FIG.2, the luminance signals Y are denoted signals Y, the chroma signals U,V, each being of 5 bit widths, are collectively denoted C-signals of the10-bit width, and the key signals K are denoted K signals.

A horizontal defocus filter (HDFF) 11 of the DME 3 is made up of anH-filter 12, for applying one-dimensional low-pass filtering to theluminance signals Y, input in the horizontal scanning sequence, anH-filter 13, for applying one-dimensional low-pass filtering to the keysignals K, input in the horizontal scanning sequence, and an H-filter14, independently interpolating the chroma signals U, V, input in thehorizontal scanning sequence, in a manner explained subsequently indetail with reference to FIGS. 3 to 6, and for applying one-dimensionallow-pass filtering to the interpolated signals. Thus, the scan converter15, downstream of the HDFF 11, is fed with 4:4:4:4 picture signals of a40 bit width.

The scan converter 15 holds picture signals, input in the horizontalscanning sequence from the HDFF 11, and scans the so-held picturesignals in the vertical direction, that is converts the scanningdirection from the horizontal to the vertical, to output the picturesignals to a vertical defocus filter VDFF 16. The scan converter 15 alsocurtails the bit width of the chroma signals U, V of the picture signalsof the 40 bit width, returned from the VDFF 16 in the vertical scanningsequence, to output the resulting picture signals to the buffer 20. Ifthe picture signals returned from the VDFF 16 are of the SD format, thescan converter 15 converts the field picture to the frame picture andinterpolates the resulting frame picture to output the resultinginterpolated picture to the buffer 20. If the picture signals, inputfrom the VDFF 16, are of the HD format, the scan converter 15 outputspicture signals in the state of the field picture to the buffer 20.

The VDFF 16 is made up by a V-filter 17, for applying one-dimensionallow-pass filtering to the luminance signals Y, input in the verticalscanning sequence, a V-filter 18 for applying one-dimensional low-passfiltering to the key signal K, input in the vertical scanning sequence,and a V-filter 19, for applying one-dimensional low-pass filtering tothe chroma signals U, V, input in the vertical scanning sequence. TheVDFF 16 returns the 4:4:4:4 picture signals of the 40-bit width, alreadysubjected to the one-dimensional low-pass filtering in the verticaldirection, to the scan converter 15.

The buffer 20 is comprised of a ZBT SRAM (Zero Bus Turnaround StaticRandom Access Memory), and writes picture signals, supplied from thescan converter 15, in accordance with the write address supplied from anaddress generator 21, while reading out the picture signals every fourpixels in accordance with the read address supplied from the addressgenerator 21 to output the so read out picture signals to aninterpolation circuit 22. Using the read address, supplied from buffer20 every four pixels, the interpolation circuit 22 interpolates thepicture signals lying at a preset position inwardly of the four pixelsto output the resulting interpolated signals to the synthesis circuit 4.Meanwhile, the address generator 21 and the interpolation circuit 22 mayalso be constituted by an FPGA (Field Programmable Gate Array).

Referring to FIGS. 3 to 6, the processing of independently interpolatingthe chroma signals U, V of the 4:2:2:4 picture signals, input to theHDFF 11, by the H-filter 14, to convert the signals into 4:4:4:4 picturesignals, is now explained. In the following description, the picturesignals are sometimes indicated 4:2:2 (Y/U/Y) or 4:4:4 picture signals,with omission of notation for the key signals. FIG. 3 shows the conceptof the processing of interpolating the chroma signals U, V.

FIG. 3A shows picture signals input to the HDFF 11 in the sequence ofhorizontal scanning. Specifically, the HDFF 11 is simultaneously fedwith luminance signals Y₀ for a certain pixel (number 0 pixel) and withchroma signals U₀ for the number 0 pixel. At the next clock, the HDFF 11is simultaneously fed with luminance signals Y_(0.5) for a pixel whichis a right-hand side neighbor to the number 0 pixel, and with chromasignals V0 for the number 0 pixel. At the next clock, the HDFF 11 issimultaneously fed with luminance signals Y₁ for the number 1 pixel,which is a right-hand side neighbor to the number 0.5 pixel, and withand with chroma signals U₁ for the number 1 pixel. In similar manner,the HDFF 11 is then simultaneously fed with luminance signals Y_(N) fora number N pixel and with chroma signals U_(N) for the number N pixeland, at the next clock, the HDFF 11 is simultaneously fed with luminancesignals Y_(N+0.5) for a number (N+0.5) pixel, which is a right-hand sideneighbor to the number N pixel, and with chroma signals V_(N) for thenumber N pixel.

It never occurs that the luminance signals Y_(N) and the chroma signalsU_(N), V_(N) for the number N pixel are input simultaneously, whilethere lack chroma signals U_(N+0.5), V_(N+0.5) for the number (N+0.5)pixel, as shown in FIG. 3A. Thus, in order to match the input timing ofthe luminance signals Y_(N) to that of the chroma signals U_(N), V_(N)and in order to unify the spatial frequencies of the luminance andchroma signals, the chroma signals U_(N+0.5), V_(N+0.5) for the number(N+0.5) pixel are interpolated. For interpolating the chroma signalsU_(N+0.5), for the number (N+0.5) pixel, chroma signals lying on theleft and right hand sides of the pixel, namely chroma signals U_(N−1)for the number (N−1) pixel, chroma signals U_(N) for the number Npixels, chroma signals U_(N+1) for the number (N+1) pixel and chromasignals U_(N+2) for the number N+2 pixels, as shown in FIG. 3B.Similarly, for interpolating the chroma signals V_(N+0.5), for thenumber (N+0.5) pixel, chroma signals lying on the left and right handsides of the pixel, namely chroma signals V_(N−1) for the number (N−1)pixel, chroma signals V_(N) for the number N pixels, chroma signalsV_(N+1) for the number (N+1) pixel and chroma signals V_(N+2) for thenumber N+2 pixels, as shown in FIG. 3C.

FIG. 4 is a block diagram showing the structure of a portion of theH-filter 14 pertinent to the processing of interpolating the chromasignals U, V of the H-filter 14. A selector 31 outputs chroma signals U,V, input sequentially from the upstream side, to the delay circuit (D)32 and to a four-point interpolation circuit 40. On the other hand,delay circuits 32 to 37 and 42 output chroma signals, input from theupstream side, with a delay of one clock period, while delay circuits33, 35 and 37 also output chroma signals, delayed by one clock period,to the four-point interpolation circuit 40. If a control signal S from aD-flipflop 41 is 0, a selector 39 sends an output of the delay circuit38, input to its own DA terminal, from a QA terminal to a delay circuit42, while sending an output of the four-point interpolation circuit 40,fed to its own DB terminal, at a QB terminal. If conversely a controlsignal S from the D-flipflop 41 is 1, the selector 39 sends an output ofthe delay circuit 38, input to its own DA terminal, from a QB terminal,while sending an output of the four-point interpolation circuit 40, fedto its own DB terminal, at the QA terminal to the delay circuit 42.Meanwhile, chroma signals U_(N) and U_(N−5) are output simultaneouslyfrom the selector 39, as shown in FIG. 3D.

The four-point interpolation circuit 40 interpolates chroma signals, bypipeline processing, which requires four clock periods, using thefollowing equation:

(Value  of  chroma  signals  to  be  in terpolated) = (t₀ * C₀ + t₁ * C₁ + t₂ * C₂ + t₃ * C₃)/(C₀ + C₁ + C₂ + C₃)where t₀ is the value of the chroma signal U_(N−1) or V_(N−1) for thepixel number (N−1) input from the delay circuit 37, t₁ is the value ofthe chroma signal U_(N) or V_(N) for the pixel number N input from thedelay circuit 35, t₂ is the value of the chroma signal U_(N+1) orV_(N+1) corresponding to the pixel number (N+1) input from the delaycircuit 33, t₃ is the value of the chroma signal U_(N+2) or V_(N+2)corresponding to the pixel number (N+2) input from the selector 31, andinterpolation coefficients C₀ to C₃ are −163, 1187, 1187 and −163,respectively. The D-flipflop 41 alternately outputs 0 and 1 as controlsignals, every clock, to the selector 39.

FIG. 5 is a block diagram showing a specified structure of thefour-point interpolation circuit 40. The four-point interpolationcircuit 40 includes multipliers 51 to 54, adders 55, 56 and a multiplier57. The multiplier 51 multiplies the value t₀ of the chroma signalU_(N−1) or V_(N−1) for the number N−1 pixel, fed from the selector 31,with an interpolation coefficient C₀, to send the resulting productvalue t₀*C₀ to the adder 55. The multiplier 52 multiplies the value t₁of the chroma signal U_(N) or V_(N) for the number N pixel, fed from thedelay circuit 33, with an interpolation coefficient C₁, to send theresulting product value t₁*C₁ to the adder 55. The multiplier 53multiplies the value t₂ of the chroma signal U_(N+1) or V_(N+1) for thenumber N+1 pixel, fed from the delay circuit 35, with an interpolationcoefficient C₂, to send the resulting product value t₂*C₂ to the adder56. The multiplier 54 multiplies the value t₂ of the chroma signalU_(N+2) or V_(N+2) for the number N+2 pixel, fed from the delay circuit37, with an interpolation coefficient C₃, to send the resulting productvalue t₃*C₃ to the adder 56. The adder 55 sums the product value t₀*C₀from the multiplier 51 to the product value t₁*C₁ from the multiplier 52to send the resulting sum value t₀*C₀+t₁*C₁ to the multiplier 57. Theadder 56 sums the product value t₂*C₂ from the multiplier 53 to theproduct value t₃*C₃ from the multiplier 54 to send the resulting sumvalue t₂*C₂+t₃*C₃ to the multiplier 57. The multiplier 57 sums the sumsthe sum value value t₀*C₀+t₁*C₁ from the adder 55 to the sum valuet₂*C₂+t₃*C₃ from the adder 56 and divides the resulting sum by the sumtotal value of the interpolation coefficients C₀ to C₃ to output theresulting quotient as a value of the chroma signal U_(N+0.5) orV_(N+0.5) for the number N+0.5 pixel.

The operation of a functional block pertinent to the processing ofinterpolating chroma signals U, V is now explained. If, at clock timingt₀, the selector 31 and the delay circuits 32 to 38 output chromasignals V₄, U₄, V₃, U₃, V₂, U₂, V₁, U₁ to the downstream side circuitry,a chroma signal V_(2.5) is interpolated by the four-point interpolationcircuit 40 in the next following four clock periods. Thus, at clocktiming t₄, a chroma signal U₃ is applied from the delay circuit 38 tothe DA terminal of the selector 39, whilst a chroma signal V_(2.5),interpolated by the four-point interpolation circuit 40, is applied toits DB terminal. At this time, in synchronism with a control signal S=0from the D-flipflop 41, the selector 39 outputs the chroma signal U₃,input to its DA terminal, to the delay circuit 42 from its QA terminal,while outputting a chroma signal V_(2.5), input to the DB terminal andinterpolated, at its QB terminal. In synchronism therewith, the delaycircuit 42 outputs the chroma signal U_(2.5), interpolated one clockbefore and delayed. So, the H-filter 14 simultaneously outputs chromasignals U_(N+0.5), V_(N+0.5), associated with the number (N+0.5) pixel,as shown in FIG. 3E.

Since the HDFF 11 eliminates high frequency components of the 4:2:2picture signals and interpolates chroma signals for converting thesignals to 4:4:4 picture signals, it becomes possible to treat theluminance signals Y and the chroma signals U, V in terms of the samespatial frequency for respective pixels. This allows to perform colorspotlight processing or trailing accompanied by color changes by way ofprocessing for picture color manipulating operations.

FIG. 6 shows a block diagram showing the configuration of the scanconverter 15 adapted for converting the scanning direction of the 4:4:4picture signals, input in the horizontal scanning sequence from the HDFF11, from the horizontal direction to the vertical direction. The scanconverter 15 includes a scan converting IC 61, formed e.g., by FPGA, andSRAMs (Synchronous Dynamic Random Access Memories) 64-1, 64-2. Based onthe horizontal scanning timing, represented by a signal REF, suppliedfrom outside, a V-scan generator 62 of the scan converting IC 61generates a signal, representing the associated vertical scanningtiming, which is output to an SDRAM controller 63 and to an SRAMcontroller 66. The SDRAM controller 63 switches the 4:4:4:4 picturesignals, input from the HDFF 11, on the field basis, to store the soread-out signals in the SDRAMs 64-1 and 64-2. The SDRAM controller 63also reads out the picture signals stored in the SDRAMs 64-1 and 64-2 ina preset sequence, as later explained, to output the so read-out signalsto the SRAM (Static Random Access Memory) 65. The SRAM 65, having acapacity per block of 2 bits*2048, uses four memories, each comprised of20 blocks, and caches picture signals, input from the SDRAM controller63, to output the so cached picture signals to the VDFF 16, undercontrol by the SRAM controller 66. A converter 67 curtails theinformation volume of chroma signals U, V of the picture signals, inputin the vertical scanning sequence from the VDFF 16, from the 10-bitwidth to the 8-bit width, in a manner to be explained in detailsubsequently by referring to FIG. 18. The converter 67 also converts thefield picture to a frame picture in case the picture signals input fromthe VDFF 16 are of the SD format, in a manner to be explained in detailsubsequently by referring to FIG. 47.

FIG. 7 shows the gross progress with time of the processing ofconverting the scanning direction to the vertical direction on the fieldbasis. In FIG. 7 ff., the buffers A and B are associated with one andthe other of the SDRAMs 64-1 and 64-2.

FIGS. 8A, 8B schematically show the relationship between the SDRAMs 64-1and 64-2, adapted for burst-transferring picture signals, stored on thefield basis, in the vertical scanning sequence, and the SRAM 65, adaptedfor caching the burst-transferred picture signals. Specifically, theSRAM 65 operates as if it is moving in the horizontal direction fromleft to right of the picture, like a caterpillar, as it scans thepicture signals, stored in the SDRAMs 64-1 and 64-2, in the verticaldirection, for caching the picture signals. It is noted that, if theamount of transfer per unit time in the inputting direction to theSDRAMs 64-1 and 64-2 in the horizontal scanning direction is equal tothat in the outputting direction to the SRAM 65 in the vertical scanningsequence, stable operation is warranted for the system. That is, thereis no risk of the read address outrunning the write address in theSDRAMs 64-1 and 64-2. Meanwhile, should there be no necessity fordemarcating the SDRAMs 64-1 and 64-2, these are referred to simply asthe SDRAM 64. As characteristic of the SDRAM, if burst transfer (autopre-charge 4 word burst) of an optimum width is carried out alternatelyon plural, such as two, banks, continuous access (read or write) iswarranted. FIG. 9 shows a timing chart of the continuous access (writeburst) in alternate burst to the two sorts of banks exploiting thesecharacteristics.

Specifically, the picture signals written in the horizontal scanningsequence on the SDRAM 64 are burst-transferred, every eight words, thatis at a rate of four words for each bank, as shown in FIG. 10. On theother hand, the picture signals, read out in the vertical scanningsequence from the SDRAM 64, are also burst-transferred, every eightwords, that is at a rate of four words from each bank, as shown in FIG.11. It is noted that a word means the information volume of 40 bitsrepresenting luminance signals Y (10 bits), chroma signals U, V (each 10bits) and key signals K (10 bits) corresponding to one pixel. If thepicture signals, burst-transferred at a rate of eight words,corresponding to two rectangular areas in FIG. 11, to the SRAM 65, andcached therein, are read out with a delay of time corresponding to fourvertical scanning, from the SRAM 65, the SRAM 65 may be of the smallestcapacity corresponding to two rectangular areas equal to 0.4% of onefield.

FIG. 12 shows an instance of two-dimensional address allocation of in2-bank 4-word burst of picture signals of the HD format (1080i×1920) tothe SDRAM 64. Referring to FIG. 12, the leading address of the burst iscontrolled, during writing, so that the address will be written at anaddress matched to horizontal scanning. In readout, a band of a burstsize width is accessed. The write addresses for the SDRAM 64 aregenerated by a counter mechanism comprised of an upper counter (ROW) anda lower counter (COLUMN), shown in FIG. 13, satisfying the followingconditions:

-   (1) Count-up is by a state machine outputting 4-word bursts as one    out of two occurrences. The next time counting occurs during    accessing to the late accessed bank.-   (2) The counter re-load and 2K up is carried out at 0x3c0. 1 k is    summed to the reload data each time lower order 0x3c0 is counted.-   (3) When the value of the upper counter reaches 540, one field is    finished.

FIG. 14 shows the sequence of continuous-readout from the SDRAM 64.Using the 4 word burst 2 bank ping-pong access, readout is to beperformed continuously so that the writing area in the SRAM 65 will bein terms of a strip (rectangular(n): n=1, 2, . . . , 1 df) comprised of540 4-word rectangular areas of FIG. 11. The readout addresses from theSDRAM 64 is generated by a counter mechanism, comprised of an upperorder counter (ROW) and a lower order counter (COLUMN), shown in FIG.15, satisfying the following conditions:

-   (1) The lower order counter is re-loaded each time. As for the    re-loading value, 4-word count-up occurs when the value of the upper    order counter reaches 540.-   (2) When the value of the lower order counter reaches 0x3c0 and the    value of the upper order counter reaches 540, the operation is    finished.-   (3) The reloading and 2K up of the upper order counter occur for    each 4 word burst ping-pong.-   (4) When the upper order counter reaches 540, the reloading of one    strip unit (4 words*540 lines) is finished.

The picture signals, read out in terms of a strip as a unit from SRAM64, are cached in the SRAM 65 and subsequently accessed. However, theaccessing sequence is fixed and completely synchronous so that fullysynchronous prediction control occurs instead of the associative controlstructure as in the case of the general-purpose cache.

FIG. 16 shows a concept of using four memories making up the SRAM 65 (2bits*2048*20 blocks) as rings each being 40 bits in width (one word)*2048. In actuality, four rings shown in FIG. 16 are stacked to form a160-bit-width*2048 caterpillar (FIG. 8B), as shown in FIG. 17A.Specifically, the 4-word rectangular area, read out from the SDRAM 64 inthe sequence shown in FIG. 15, is sequentially written word-by-word inthe rings 0 to 3 as shown in FIG. 17B. After delay by time correspondingto three vertical scanning, the so written words are read out in thecircumferential direction of the ring, as shown in FIG. 17C. By theabove-described sequence of operations, it becomes possible to changethe scanning direction of the picture signals from the horizontal to thevertical in real-time to output the picture signals to the downstreamside VDFF 16. The picture signals, input to the VDFF 16, are processedwith one-dimensional low-pass filtering in the vertical direction andagain input to the scan converter 15 so as to be thence sent to theconverter 67.

The processing of the converter 67 in converting the 4:4:4:4 picturesignals of the 40 bit width, input in the vertical scanning sequencefrom the VDFF 16, into picture signals of 36 bit width, with a view toadapting the signals to the downstream side buffer 20 employing eightZBT SRAMs of 36 bit widths, is hereinafter explained.

Referring to FIG. 18, the converter 67 converts the picture signals(Y/U/V/K) to a 36 bit width by curtailing the values of the chromasignals U, V in the 4:4:4:4 picture signals of the 40 bit width (made upof 10 bits of the luminance signals Y, 10 bits of chroma signals U, 10bits of chroma signals V and 10 bits of key signals K), input from theVDFF 16 in the vertical scanning sequence, which chroma signalsultimately revert the spatial frequency characteristics to one-half, torespective 8 bits by rounding or truncation, to output the resultingsignals to the downstream side buffer 20. Meanwhile, the curtailment ofthe bit width of the chroma signals U, V is not limited to that to 8 bitwidth. Specifically, the curtailing width may be appropriately changed,such as by curtailing the chroma signals U to 9 bits and curtailing thechroma signals V to 7 bits.

With the above-described converter 67, it is possible to adapt the bitwidth of the picture signals of the picture signals (Y/U/V/K) to the ZBTSRAM of the 36-bit width in the downstream side buffer 20, withoutimpairing the information volume of the luminance signals Y nor that ofthe key signals critical in digital video effect.

FIG. 19 shows a detailed exemplary structure of the buffer 20, made upof four units U0, U1, L0 and L1, that may be read out simultaneously.FIG. 20 shows an exemplary structure of the unit U0, which is of adouble-buffer structure comprised of an A-buffer comprised of an SRAM73-U0-A and a B-buffer comprised of an SRAM73-U0-B. Thus, the unit U0 iscapable of performing two-dimensional readout and concurrent writing.Similarly, each of the units U0 to L1 is also of the double bufferstructure to provide for two-dimensional readout and concurrent writing.Meanwhile, if there is no necessity of demarcating the SRAM 73-U0-A to73-L1-B from each other, the SRAMs are collectively referred to as SRAM73.

FIG. 21 shows allocation of picture signals input from the scanconverter 15 to the units U0 to L1. That is, in writing the picturesignals of the even field, output by the scan converter 15, in thebuffer 20, the two neighboring pixels on the number m horizontalscanning line, where m=0, 2, 4, . . . , and two neighboring pixels onthe number (m+2) horizontal scanning line directly below the firststated pixels, totaling at four pixels, are written in the A-buffers ofrespective different units U0 to L1, as shown in FIG. 21A. Also, inwriting the picture signals of the odd field, output by the scanconverter 15, in the buffer 20, the two neighboring pixels on the number(m+1) horizontal scanning line, where m=0, 2, 4, . . . , and twoneighboring pixels on the number (m+3) horizontal scanning line directlybelow the first stated pixels, totaling at four pixels, are written inthe B-buffers of respective different units U0 to L1, as shown in FIG.21B. By writing the four pixels, neighboring to one another in thevertical and transverse directions, in the respective different units U0to L1, these can be read out simultaneously, thus enabling the operationof interpolating a pixel, lying centrally of the four pixels with thepicture signals of the four pixels, to be performed efficiently.

Referring to FIGS. 22 to 28, an ex-area data band (black area), to beset around the data area carrying the written picture signals (realimage data) in an effective access area of the buffer 20, is explainedwith reference to FIGS. 22 to 28. FIG. 22 shows a coordinate system ofread-out addresses, also termed linear addresses, as set in the buffer20, while FIG. 23 shows the state in which even-field picture signalsare being written in the data area (real image area) shown in FIG. 22.

In general, in reading out picture signals written in the buffer 20, thereadout addresses on the buffer 20 are determined based on the addresseson the display when the picture signals processed with digital effect bythe DME 3 are demonstrated on a display. The addresses on the displayare herein termed screen addresses. The relationship between the screenaddresses and the read addresses will be explained subsequently indetail by referring to FIG. 29.

If the readout address [X, Y] are determined at the positions indicatedwith x in FIG. 24, the picture signals of the four pixels lying at upperand lower and left and right positions relative to the readout address[X, Y] are read out and sent to the interpolation circuit 22 tointerpolate the picture signals of the pixel lying at the readoutaddress [X, Y]. It should be noted that the interpolation processingemploying four pixels is for picture signals of the HD format and thatthe interpolation processing employing 16 pixels is applied to thepicture signals of the SD format.

Meanwhile, if the position indicated x in FIG. 25 is the read address[X, Y], there lack the four pixels at upper and lower and left and rightpositions thereof, so that processing different from the usualinterpolation processing employing four pixels is needed. Thus, giventhe read address [X, Y], it is necessary to determine whether or notusual interpolation processing can be applied for the read address [X,Y], such that it becomes necessary to provide a dedicated circuit formaking a corresponding decision. So, with a view to dispensing with suchdedicated circuit, an ex-area data band is set in the buffer 20.Specifically, dummy output signals corresponding to two pixels arewritten in each of the upper and lower positions and the left and rightpositions of the data area in which to write picture signals (real imagearea), as shown in FIGS. 26 and 27, to set the ex-area data band (blackarea). Meanwhile, FIG. 27 shows the state in which the picture signalsof the even field are written in the data area (real image area) of FIG.26, with the ex-area data band being set therearound.

It is now proved that, insofar as the recording capacity is concerned, adata area in which to write picture signals and an ex-area band can beset in the buffer 20. There are provided eight SRAMs 73-U0-A to 73-L1-Bin the buffer 20, as shown in FIG. 19 and picture signals of the fieldpicture are adapted to be stored in four of these SRAMs. The effectiveaccess area of one of the SRAMs 73 is 256 k words=256*1024 words=262144words. The data area and the ex-area data band, to be written therein,are ¼ of picture signals of the field picture (540×1920) and each twopixels on the upper, lower, left and right sides thereof, so that thecapacity required is 544*1924/4=261664 words, which may be fully storedin one effective access area of the SRAM 73. Thus, insofar as therecording capacity is concerned, it is possible to set the x-area databand in the buffer 20.

By setting the data area and the ex-area data band within the effectiveaccess area of the buffer 20, four pixels are present on the upper,lower, left and right sides of a position occasionally set as a readaddress [X, Y] as indicated by a mark x in FIG. 28, so that routineinterpolation processing employing four pixels can be applied. Thus,given the readout address [X, Y], it is unnecessary to verify whether ornot the routine interpolation processing is applicable to the readaddress [X, Y] to render it possible to omit the dedicated circuitadapted for making the decision. The read address that can be generatedis−960.5<X<960.5and−540.5<Y<540.5.

Before proceeding to description of the address generator 21 furnishingthe read address to the buffer 20, the relationship between the screenaddress and the read address is explained in detail with reference toFIG. 29. FIG. 29A shows the coordinate system of the readout address(X_(m), Y_(m), T) set in the buffer 20. This readout address isequivalent to the above-mentioned read address [X, Y]. In the coordinatesystem of the read address, the point of origin is set at the center ofa picture. Meanwhile, T indicates the lighting modulation axis (T-axis)used for specifying the lighting occasionally added to the picture. FIG.29B shows the coordinate system of the screen address (H, V). In thecoordinate system of the screen address, the point of origin is at anupper left side of a picture. In the coordinate system of the readingaddress, points a to d are associated with points a′ to d′ of thecoordinate system of the read addresses, respectively.

The screen address (H, V) corresponds to the read address (X_(m), Y_(m),T) transformed using a 3×3 transformation matrix A. Thus, the readaddresses (X_(m), Y_(m), T) can be calculated in a reverse sequence,that is by multiplying the sequentially scanned screen address (H, V)with an inverse matrix A⁻¹ of the transformation matrix A. Specifically,the read addresses (X_(m), Y_(m), T) is calculated as indicated by thefollowing equation 1:

$\begin{matrix}\begin{matrix}{{Xm} = {\frac{{a_{11} \cdot H} + {a_{12} \cdot V} + a_{13}}{{a_{31} \cdot H} + {a_{32} \cdot V} + a_{33}} = \frac{X\left( {H,V} \right)}{Z\left( {H,V} \right)}}} \\{{Ym} = {\frac{{a_{21} \cdot H} + {a_{22} \cdot V} + a_{23}}{{a_{31} \cdot H} + {a_{32} \cdot V} + a_{33}} = \frac{Y\left( {H,V} \right)}{Z\left( {H,V} \right)}}} \\{T = \frac{\mspace{76mu}{{\left( {{p \cdot a_{11}} + {q \cdot a_{21}}} \right) \cdot H} + \;{\left( {{p \cdot a_{12}} + {q \cdot a_{22}}} \right) \cdot V} + {p \cdot a_{13}} + {q \cdot a_{23}}}}{{a_{31} \cdot H} + {a_{32} \cdot V} + a_{33}}} \\{= {\frac{T\left( {H,V} \right)}{Z\left( {H,V} \right)}.}}\end{matrix} & (1)\end{matrix}$

Meanwhile, the effect parameters a₁₁ to a₃₃ are components of theinverse matrix A⁻¹, as indicated by the equation 2:

$\begin{matrix}{A^{- 1} = {\begin{bmatrix}a_{11} & a_{12} & a_{13} \\a_{21} & a_{22} & a_{23} \\a_{31} & a_{32} & a_{33}\end{bmatrix}.}} & (2)\end{matrix}$

It is noted that rotation coefficients p, q of the lighting modulationaxis T are given by p=cosè and q=sinè.

Thus, the read addresses (X_(m), Y_(m), T) may be calculated usingfunction values X(H, V), Y(H, V), T(H, V) and Z(H, V) having the screenaddress (H, V) as parameters. Meanwhile, the read address is calculatedfrom one pixel of the sequentially scanned screen addresses to another,that is from one clock to another. It the function values X(H, V), Y(H,V), T(H, V) and Z(H, V) are calculated for all pixels of the screenaddresses to calculate the read addresses, the processing is voluminous,thus necessitating a dedicated circuit for making these calculations.So, function values X(0, 0), Y(0, 0), T(0, 0), Z(0, 0), X(0, 539), Y(0,539), T(0, 539), Z(0, 539), X(1919, 0), Y(1919, 0), T(1919, 0), Z(1919,0), X(1919, 539), Y(1919, 539), T(1919, 539) and Z(1919, 539), referredto below as function values X(0, 0) to Z(1919, 539), are calculated atthe outset for four terminal points of the screen addresses, namely aleft upper point (0, 0), a left lower point (0, 539), a right upperpoint (1919, 0) and a right lower point (1919, 539), as shown in FIG.30. The function values X(H, V), Y(H, V), T(H, V) and Z(H, V) of theremaining pixels of the screen addresses are interpolated, using thefunction values X(0, 0) to Z(1919, 539), calculated for the fourterminal points, to calculate the corresponding read addresses.

The processing of using the function values X(0, 0) to Z(1919, 539),calculated for the four terminal points of the screen addresses, tointerpolate the function values X(H, V), Y(H, V), T(H, V) and Z(H, V) ofthe remaining pixels of the screen addresses, is termed below thesuper-interpolation. In particular, the interpolation processing in thevertical direction between the left upper point (0, 0) and the leftlower point (0, 539) or between the right upper point (1919, 0) and theright lower point (1919, 539) is termed the super-interpolation (V), andthe processing of interpolation in the horizontal direction employingthe function values of the left and right end points on the horizontalscanning lines, obtained e.g., by the super-interpolation (V), is termedthe super-interpolation (H).

Referring to FIG. 31, the processing timing of the super-interpolationis explained with reference to FIG. 31. If super-interpolation isapplied to a given field picture, the function values X(0, 0) to Z(1919,539) are calculated at the outset for each of the four terminal pointsof the screen addresses, before the time of the field directly previousto the field picture, and are held at a preset register, which will beexplained subsequently. The super-interpolation (V) is executed at aninitial stage of the horizontal blanking period (BLANK(H)), insynchronism with the Enable of the timing signal VMIX, whilesuper-interpolation (H) is executed every clock during the period ofhorizontal scanning (ACTIVE AREA) of the screen addresses in synchronismwith the Enable of the timing signal HMIX. That is, the execution timingof the super-interpolation (H) differs from that of thesuper-interpolation (V).

FIG. 32 shows an exemplary structure of the address generator 21. Aregister calculating block 91 calculates function values X(0, 0) toZ(1919, 539) of the four terminal points of the screen addresses toroute the so calculated values to a super-interpolation block 93. Themixer coefficient block 92 sends mixer coefficients, held at the outsetin an enclosed register, to the super-interpolation block 93. Using thefunction values X(0, 0) to Z(1919, 539) of the four terminal points ofthe screen addresses, supplied form the register calculating block 91,and the mixer coefficients, supplied from the mixer coefficient block92, the super-interpolation block 93 executes the super-interpolation(H) and the super-interpolation (V) and interpolates the correspondingfunction values X(H, V), Y(H, V), T(H, V) and Z(H, V) in the pixelsother than the four terminal points on the screen addresses so obtainedto output the interpolated values to a read address operating block 94.Using the function values X(H, V), Y(H, V), T(H, V) and Z(H, V),associated with all of the pixels of the screen addresses, input fromthe super-interpolation block 93, the read address operating block 94generates read addresses, which are output to the buffer 20.

FIG. 33 shows an illustrative structure of the super-interpolation block93. The super-interpolation block 93 is made up of a block interpolatingthe function value X(H, V), a block interpolating the function valueY(H, V), a block interpolating the function value T(H, V) and a blockinterpolating the function value Z(H, V).

A REG_V_START_XL register 101-X of the block interpolating the functionvalue X(H, V) holds the function value X(0, 0) for the left upper point(0, 0) supplied from the register calculating block 91, and outputs theso held value to a terminal A of a selector 107-X. A REG_V_START_XRregister 102-X of the block holds the function value X(1919, 0) for theright upper point (1919, 0) supplied from the register calculating block91 and outputs the so held value to a terminal B of the selector 107-X.An FF_H_START_X register 103-X holds an output of a mixer 111-X inputvia B-terminal of a selector 112-X to output the so-held value to theB-terminal of a selector 108-X. An FF_H_END_XL register 104-X holds anoutput of a mixer 111-X input via B-terminal of the selector 112-X tooutput the so-held value to the B-terminal of a selector 110-X. AREG_V_END-XL register 105-X holds the function value X(0, 539) for theleft lower point (0, 539) supplied from the register calculating block91 to output the so held value to the B-terminal of a selector 109-X. AREG_V_END_XR register 106-X holds the function value X(1919, 539) forthe right lower point (1919, 539) supplied from the register calculatingblock 91 to output the so held value to the A-terminal of a selector109-X.

The selectors 107-X to 110-X output inputs to the A or B terminals tothe downstream circuitry. The selector 112-X routes an output of themixer 111-X to an FF_H_START_X register 103-X or to an FF_H_END_Xregister 104-X. If the output of the selector 108-X input to the Aterminal is A, the output of the selector 110-X input to the B terminalis B and the mixer coefficient supplied from the mixer coefficient block92 is kn, the mixer 111-X outputs an interpolated value C of thefollowing equation:Interpolated value C=A·(1.0−k _(n))+B·k _(n)every clock to the downstream side circuitry. In actuality, thefollowing equation:Interpolated value C=k _(n)(B−A)+Ais used in order to diminish the number of times of multiplication byone.

Meanwhile, the structure of each block for interpolating each of thefunction values Y(H, V), T(H, V) and Z(H, V) is the same as thestructure of the block for calculating the function value X(H, V) andhence the corresponding description is omitted for simplicity. It shouldbe noted that the relation of correspondence between the functionREG_V_START_XL register 101X to REG_V_END-ZR register 106-Z and thefunction values X(0, 0) to Z(1919, 539) these registers hold is as shownin FIG. 34. The registers enclosed in the mixer coefficient block 92,and the mixer coefficients held therein, are shown in FIG. 35.

The operation of the super-interpolation block 93 is now explained. Itis assumed that the function REG_V_START_XL register 101X toREG_V_END_ZR register 106-Z are fed with corresponding function values(0, 0) to (1919, 539) from the register calculating block 91.

First, the vertical component of the screen address is initialized toV=0, and super-interpolation (V) is started in synchronism with Enableof the timing signal VMIX. First, for executing the super-interpolation(V) of the left end point (0, V) of the screen address, switching etc ismade at each block so that the input originating point and outputdestination point of the function values for the mixers 111-X to 111-Zwill be as shown in FIG. 36. Specifically, selectors 107-X to 110-X and112X are switched in a block interpolating the function values X(H, V),as shown in FIG. 37. This causes the function value X(0, 0) for the leftupper point (0, 0), held in the function REG_V_START_XL register 101-X,to be input to a terminal A of the mixer 111-X, while causing thefunction value X(0, 539) for the left lower point (0, 539), held in thefunction REG_V_END_XL register 105X, to be input to a terminal B of themixer 111-X. The mixer 111-X is also fed with mixer coefficients fromthe mixer coefficient block 92. The mixer 111-X interpolates thefunction values X(0, V) pertinent to the left end point X(0, V) of thescreen address. The interpolated function values X(0, V) is latched viaselector 12-X in an FF_H_START_X register 103-X. Similar processing isapplied to the remaining blocks, whereby function values Y(0, V), T(0,V) and Z(0, V) pertinent to the left end point (0, V) of the screenaddress are latched in associated FF_H_START_Y register 103-Y toFF_H_START_Z register 103-Z.

Then, for executing super-interpolation (V) of the right end point(1919, V) of the screen address, switching etc is made at each block sothat the input originating point and output destination point of thefunction values for the mixers 111-X to 111-Z will be as shown in FIG.38. Specifically, selectors 107-X to 110-X and 112X are switched in ablock interpolating the function values X(H, V), as shown in FIG. 39.This causes the function value X(1919, 539) for the right upper point(1919, 539), held in the REG_V_START_XR register 102-X, to be input tothe terminal A of the mixer 111-X, while causing the function valueX(1919, 539) for the right lower point (1919, 539), held in the functionREG_V_END_XR register 106X, to be input to a terminal B of the mixer111-X. The mixer 111-X is also fed with mixer coefficients from themixer coefficient block 92. The mixer 111-X interpolates the functionvalues X(1919, V) pertinent to the right end point X(1919, V) of thescreen address. The interpolated function values X(1919, V) are latchedvia selector 112-X in an FF_H_END_X register 104-X. Similar processingis applied to the remaining blocks, whereby function values Y(1919, V),T(1919, V) and Z(1919, V) pertinent to the right end point (1919, V) ofthe screen address are latched in associated FF_H_END_Y register 104-Yto FF_H_END-Z register 104-Z.

The processing up to this point is executed during the horizontalblanking period. Subsequently, the horizontal component H of the screenaddress is initialized in synchronism with an Enable of the timingsignal HMIX, so that H=0 to start super-interpolation (H). For executingthe super-interpolation (H), switching etc is made at each block so thatthe input originating point and output destination point of the functionvalues for the mixers 111-X to 111-Z will be as shown in FIG. 40.Specifically, selectors 108-X to 110-X are switched in a blockinterpolating e.g., the function values X(H, V), as shown in FIG. 41.This causes the function value X(0, V) for the left end point (0, V),held in the FF_H_START_X register 103-X, to be input to the terminal Aof the mixer 111-X, while causing the function value X(1919, V) for theright end point (1919, V), held in the FF_H_END-X register 104X, to beinput to a terminal B of the mixer 111-X. The mixer 111-X is fed withmixer coefficients from the mixer coefficient block 92 on the clockbasis. The mixer 111-X sequentially interpolates function values X(H, V)for the left end point (0, V) up to the right end point (1919, V) on theclock basis to send the so interpolated function values to the readaddress operating block 94. Similar processing is performed for theremaining blocks so that function values Y(H, V), T(H, V) and Z(H, V)from the left end point (0, V) to the right end point (1919, V) areinterpolated and sent to the read address operating block 94.

The processing up to this stage is executed during the horizontalscanning period following initialization of the horizontal component Hof the screen address. The vertical component V then is incremented by 1to repeat the processing as from the aforementioned super-interpolation.When the vertical component V reaches 540, the super-interpolation forthe field being processed comes to a close so that the next field is nowprocessed in similar manner.

Since the super-interpolation (V) is executed during the horizontalblanking period and the super-interpolation (H) is executed during thehorizontal scanning period, the super-interpolation (V) and thesuper-interpolation (H) can be executed using the same circuit(super-interpolation block 93) in common.

The interpolation circuit 22 is now explained with reference to FIG. 42.If the picture signals stored in the buffer 20 are of the HD format, theinterpolation circuit 22 executes four-point interpolation processing,employing four-pixel picture signals, with an operating frequency of74.25 MHz. On the other hand, if SD format picture signals arefield/frame converted and stored in the buffer 20, 16-pointinterpolation processing, employing 16-pixel picture signals, is carriedout at an operating frequency of 54 MHz (quadrupled speed of the usualoperating frequency of 13.5 MHz used in processing SD format picturesignals).

FIG. 42 shows an exemplary structure of the interpolation circuit 22including a proportional distribution circuit for the vertical direction121, a proportional distribution circuit for the vertical direction 122and a proportional distribution circuit for the horizontal direction123. The proportional distribution circuit for the vertical direction121 proportionally distributes picture signals of two verticallyneighboring pixels, input simultaneously from the units U0, L0 of thebuffer 20, to calculate an interpolated value TA of picture signalslying intermediate between the two pixels, whilst the proportionaldistribution circuit for the vertical direction 122 proportionallydistributes picture signals of two vertically neighboring pixelssimultaneously input from the units U1, L1 of the buffer 20 to calculatethe interpolated value TB of the picture signals lying intermediatebetween the two pixels. The proportional distribution circuit for thehorizontal direction 123 proportionally distributes the interpolatedvalues TA input from the proportional distribution circuit for thevertical direction 121 and the interpolated values TB input from theproportional distribution circuit for the vertical direction 122.

FIG. 43 shows an exemplary structure of the proportional distributioncircuit for the vertical direction 121, which proportional distributioncircuit 121 is fed not only with picture signals of two verticallyneighboring pixels, simultaneously sent from units U0, L0 of the buffer20, but also with four-bit position information r, indicating theposition in the vertical direction of the interpolating point betweenthe two pixels, and with a signal sel controlling the selectors 143,144. The picture signals from the unit U0 are input to a delay circuit(D) 141 from the unit U0, while the picture signals from the unit L0 areinput to a delay circuit 142. The position information r is input to adelay circuit 148. The signal sel is input to the delay circuit 152. Thedelay circuit (D) 141 delays the picture signals from the unit U0 by apreset clock period to output the picture signals from the unit U0 to aterminal a of the selectors 143 and to a terminal_(b) of the selector144. The delay circuit 142 delays the picture signals from the unit L0by a preset clock period to output the delayed signals to a terminal_(b)of the selector 143 and to a terminal a of the selector 144. Based onthe signal sel, input from the delay circuit 152, the selector 143outputs the picture signals from the unit U0, input to the terminal a,or the picture signals from the unit L0, input to the terminal b, to amultiplier 145. Based on an inverted version of the signal sel, inputfrom a NOT circuit 153, the selector 144 outputs the picture signalsfrom the unit L0, input to the terminal_(a), or the picture signals fromthe unit U0, input to the terminal b, to a multiplier 146. Thus, one ofthe multipliers 145, 146 is fed with picture signals from the unit U0,with the other of the multipliers 145, 146 being fed with the picturesignals from the unit L0. The values of the picture signals input to themultiplier 145 and to the multiplier 146 are termed A and B,respectively. The multiplier 145 multiplies a value (16−r), input fromthe delay circuit 151, with the value A of the picture signals inputfrom the selector 143, to output the resulting product to an operatingunit 147. The multiplier 146 multiplies a value r of the positioninformation, input from a delay circuit 149, with the value B of thepicture signals, input from the selector 144, to output the resultingproduct value to an operating unit 147, which operating unit sums theoutput of the multiplier 145 to the output of the multiplier 146 anddivides the resulting sum with 16.

The proportional distribution circuit for the vertical direction 121,configured as described above, outputs the interpolated value TA for thevertical direction, represented by the following equation:(interpolated value) TA=(A*(16−r)+B*r)/16to the proportional distribution circuit for the horizontal direction123.

Meanwhile, the structure of the proportional distribution circuit forthe vertical direction 122 is similar to that of the proportionaldistribution circuit for the vertical direction 121 and hence is notexplained specifically.

FIG. 44 shows an exemplary structure of the proportional distributioncircuit for the horizontal direction 123. The proportional distributioncircuit for the horizontal direction 123 is fed not only with theinterpolated value TA for the vertical direction from the proportionaldistribution circuit for the vertical direction 121 and with theinterpolated value TB for the vertical direction from the proportionaldistribution circuit for the vertical direction 122, but also with thefour-bit position information r′, indicating the position in thehorizontal direction of the interpolating point, which four-bit positioninformation r′ is input to interpolation coefficient furnishing circuits171, 172. A multiplier 161 multiplies the interpolated value TA for thevertical direction from the proportional distribution circuit for thevertical direction 121 with an interpolation coefficient Ci, input fromthe interpolation coefficient furnishing circuit 171, to output theresulting product to a register (R0) 163. A multiplier 162 multipliesthe interpolated value TB for the vertical direction from theproportional distribution circuit for the vertical direction 122 withthe interpolation coefficient Ci input from the interpolationcoefficient furnishing circuit 172 to output the result to the register(R1) 164. An adder 165 sums an output of the register (R0) 163 to anoutput of a register (R1) 164 to output the result to a register (R2)166. An adder 167 sums the output of the register (R2) 166 to an outputof a register (R3) 168, which is the output of the adder 167 itself, oneclock period before, as held by the register (R3) 168, to output theresult to the register (R3) 168 and to a divider 169. The divider 169divides the output of the adder 167 (cumulative value of output of theadder 165 during a preset period) with the sum ΣCi of the interpolationcoefficients to output the result to a register (R4) 170. The register(R0) 163, register (R1) 164, register (R2) 166 and the register (R3) 168output inputs from respective upstream side components with a delay ofpreset clock periods. The register (R3) 168 is reset responsive to RSR_Rsignal to initialize the value it holds. The register (R4) 170 outputsthe value it holds responsive to an EN signal. The interpolationcoefficient furnishing circuits 171, 172 send interpolation coefficientCi, corresponding to the four-bit position information r′, indicatingthe position of the interpolation point in the horizontal direction, tothe multipliers 161, 162.

The proportional distribution circuit for the horizontal direction 123,constructed as described above, outputs an interpolated value for thehorizontal direction, represented by the following equation:interpolated value X=Σ(Ci*Ti)/ΣCiwhere i=0, 1 for four-point interpolation and i=0, 1, 2, . . . , 7 for16-point interpolation. FIG. 45 shows the value of the interpolationcoefficients Ci in case of 16-point interpolation of field/frameconverted SD format picture signals.

The operation of the interpolation circuit 22 is now explained. First,the four-point interpolation in case the HD format picture signals arestored in the buffer 20 is explained. The HD format picture signals arestored, in terms of a field picture as a unit, so that four pixelsneighboring to one another in the up-and-down direction and in theleft-and-right direction are separately stored in the units U0, U1, L0and L1 of the buffer 20, as shown in FIG. 21, so that, in interpolatingpicture signals corresponding to an interpolation point indicated by amark x of an even field shown in FIG. 46A, the picture signals of thefour pixels lying on the upper and lower sides and on the left and rightsides of the interpolation point can be read out simultaneously in oneclock period. Of the picture signals, read out simultaneously in oneclock period from the units U0, U1, L0, L1, termed signals U0, U1, L0,L1, the signals U0 and L0 are sent to the proportional distributioncircuit for the vertical direction 121, while the signals U1, L1 aresent to the proportional distribution circuit for the vertical direction122. The proportional distribution circuit for the vertical direction121 proportionally distributes the signals U0, L0, responsive to theposition information r for the vertical direction of the interpolationpoint, to send the resulting interpolated value TA for the verticaldirection to the proportional distribution circuit for the horizontaldirection 123. The proportional distribution circuit for the verticaldirection 122 proportionally distributes the signals U1, L1, responsiveto the position information r for the vertical direction of theinterpolation point, to send the resulting interpolated value TB for thevertical direction to the proportional distribution circuit for thehorizontal direction 123. The proportional distribution circuit for thehorizontal direction 123 proportionally distributes the interpolatedvalues TA, TB for the vertical direction, responsive to the positioninformation r′ for the horizontal direction of the interpolation point,to obtain an interpolated value for the interpolation point x.Meanwhile, the operation for picture signals of the odd field, shown inFIG. 46B, is the same as that described above and hence is not explainedspecifically.

Before proceeding to description of the 16-point interpolationprocessing in case field/frame converted SD format picture signals arestored in the buffer 20, the SD format picture signals as stored areexplained, taking 480i×720 SD format picture signals, as an example, byreferring to FIG. 47.

Before being fed to the buffer 20, the SD format picture signals areconverted by a converter 67 of the scan converter 15, into a 480×720frame picture, by synthesizing an even field picture, shown in FIG. 47A,made up of pixels denoted ∘ in FIG. 47A, and an odd field picture, madeup of pixels denoted □ in FIG. 47A. Additionally, from the verticallyneighboring pixels, indicated by ∘ and □, pixels lying intermediatebetween the two pixels, indicated Ä in FIG. 47B, are interpolated, forconversion to a 960×720 frame picture. The SD format picture signals,converted into the 960×720 frame picture, are stored as shown in FIG.48, that is such that the four neighboring pixels on the upper and lowersides and on the left and right sides are separately stored in the unitsU0, U1, L0 and L1 of the buffer 20, as in the case of the HD formatfield picture stored in the buffer 20.

The concept of the operation of the 16-point interpolation processing bythe interpolation circuit 22 is now explained. For example, ininterpolating picture signals corresponding to the point ofinterpolation, shown by a mark x in FIG. 49, eight neighboring pixels ofan upper row with respect to the point of interpolation and eightneighboring pixels of a lower row with respect to the point ofinterpolation, totaling at 16 pixels (16 pixels encircled by ahorizontally elongated rectangle) are read out and proportionallydistributed. Specifically, the picture signals of the eight pixels ofthe upper row and those of the associated eight pixels of the lower roware proportionally distributed by the proportional distribution circuitfor the vertical direction 121 and by the proportional distributioncircuit for the vertical direction 122, respectively, to calculateinterpolated values T0 to T7 for the vertical direction, as shown inFIG. 50. The interpolated values T0 to T7 for the vertical direction aremultiplied by the proportional distribution circuit for the horizontaldirection 123 with interpolation coefficients C₀ to C₇, as shown in FIG.51, to give a sum total Σ(Ti*Ci), which then is divided by the sum totalΣCi of the interpolation coefficients Ci to calculate an interpolatedvalue of the point of interpolation x. In the present case, i=0, 1, . .. , 7.

Referring to FIGS. 52 to 54, the operational timing of the 16-pointinterpolation processing of the interpolation circuit 22 executed withthe operating frequency of 54 MHz is explained. Since the units U0, U1,L0 and L1 of the buffer 20 permit concurrent readout, four pixels areread at a time sequentially in the 16-point interpolation processingeach clock period. That is, if, as shown in FIG. 52A, the picturesignals of 16 pixels, used for interpolation, and which are separatelystored in the units U0, U1, L0 and L1 of the buffer 20, are depicted a0to a15 , the picture signals a0, a1, a8 and a9 shown in FIG. 52B areread at a number 0 timing (cycle 0), the picture signals a2, a3, a10 anda11 shown in FIG. 52C are read at a number 2 timing (cycle 1), thepicture signals a4, a5, a12 and a13 shown in FIG. 52D are read at anumber 3 timing (cycle 2), and the picture signals a6, a7, a14 and a15shown in FIG. 52E are read at a number 4 timing (cycle 3). The picturesignals a0, a8, read out at the number 0 timing (cycle 0) are input tothe proportional distribution circuit for the vertical direction 121,whilst the picture signals a1, a9 are input to the proportionaldistribution circuit for the vertical direction 121. The picture signalsa2, a10, read out at the number 1 timing (cycle 1) are input to theproportional distribution circuit for the vertical direction 121, whilstthe picture signals a3, a11 are input to the proportional distributioncircuit for the vertical direction 122. The picture signals a4, a12,read out at the number 2 timing (cycle 2) are input to the proportionaldistribution circuit for the vertical direction 121, whilst the picturesignals a5, a13 are input to the proportional distribution circuit forthe vertical direction 122. The picture signals a6, a14 read out at thenumber 3 timing (cycle 3) are input to the proportional distributioncircuit for the vertical direction 121, whilst the picture signals a7,a15 are input to the proportional distribution circuit for the verticaldirection 122.

FIGS. 53A, 53B show the operating timing of the proportionaldistribution circuits for the vertical direction 121, 122. Theproportional distribution circuit for the vertical direction 121sequentially outputs the interpolated values TA for the verticaldirection to the proportional distribution circuit for the horizontaldirection 123 at a timing delayed from the input timing from the unitsU0, L0 of the buffer 20 by four clocks. Specifically, the proportionaldistribution circuit for the vertical direction 121 outputs aninterpolated value Ta0, corresponding to proportional distribution ofthe picture signals a0, a8, at a number 5 timing (cycle 5), whileoutputting an interpolated value Ta2, corresponding to proportionaldistribution of the picture signals a2, a10, at a number 6 timing (cycle6), an interpolated value Ta4, corresponding to proportionaldistribution of the picture signals a4, a12, at a number 7 timing (cycle7) and outputting an interpolated value Ta6, corresponding toproportional distribution of the picture signals a6, a14, at a number 8timing (cycle 8). Similarly, the proportional distribution circuit forthe vertical direction 122 sequentially outputs the interpolated valuesTB for the vertical direction to the proportional distribution circuitfor the horizontal direction 123 at a timing delayed from the inputtiming from the units U1, L1 of the buffer 20 by four clocks.Specifically, the proportional distribution circuit for the verticaldirection 122 outputs an interpolated value Ta1, corresponding toproportional distribution of the picture signals a1, a9, at a number 5timing (cycle 5), while outputting an interpolated value Ta3,corresponding to proportional distribution of the picture signals a3,a11, at a number 6 timing (cycle 6), an interpolated value Ta5,corresponding to proportional distribution of the picture signals a5,a13, at a number 7 timing (cycle 7) and outputting an interpolated valueTa7, corresponding to proportional distribution of the picture signalsa7, a15, at a number 8 timing (cycle 8).

FIG. 54 shows the operating timing of the proportional distributioncircuit for the horizontal direction 123. The proportional distributioncircuit for the horizontal direction 123 outputs interpolated values Xevery for clock periods. Specifically, the multiplier 161 multiplies theinterpolated values Ta₀, Ta₂, Ta₄ and Ta₆ for the vertical direction,sequentially input at the number 5 to number 8 timings, withinterpolation coefficients C₀, C₂, C₄ and C₆, respectively to output theresults of multiplication to the register (R0) 163. The register (R0)163 sequentially outputs the results of multiplication Ta₀*C₀, Ta₂*C₂,Ta₄*C₄, Ta₆*C₆ to the adder 165, at the number 8 to number 11 timings,delayed from the input timing by three clock periods. Similarly, themultiplier 162 multiplies the interpolated values Ta₁, Ta₃, Ta₅ and Ta₇for the vertical direction, sequentially input at the number 5 to number8 timings, with interpolation coefficients C₁, C₃, C₅ and C₇,respectively to output the results of multiplication to the register(R1) 164. The register (R1) 164 sequentially outputs the results ofmultiplication Ta₁*C₁, Ta₃*C₃, Ta₅*C₅, Ta₇*C₇ to the adder 165, at thenumber 8 to number 11 timings, delayed from the input timing by threeclock periods.

The adder 165 sums the products Ta₀*C₀ and Ta₁*C₁ the products Ta₂*C₂and Ta₃*C₃, the products Ta₄*C₄ and Ta₅*C₅ and the products Ta₆*C₆ andTa7*C₇, sequentially input from the multipliers 161, 162 at the number 8to number 11 timings, to output the results of summation to the register(R2) 166. The register (R2) 166 sequentially outputs the results ofsummation Ta₀*C₀+Ta₁*C₁, Ta₂*C₂+Ta₃*C₃, Ta₄*C₄+Ta₅*C₅ and Ta₆*C₆+Ta₇*C₇to the adder 167 at the number 9 to the number 12 timings, delayed byone clock period from the input timing. The adder 167 sums the resultsof summation, sequentially input from the adder 165 at the number 9 tonumber 12 timings, to the output of the adder 167, one clock periodbefore, input from the register (R3) 168, to send the results ofsummation to the register (R3) 168 and to the divider 169. Meanwhile,the register (R3) 168 is initialized in synchronism with an RST_R signalinput every four clock periods. Consequently, the adder 167 outputs atthe number 13 timing the cumulative value of the results of summation,sequentially input from the adder 165 at the number 9 to number 12timings. The divider 169 divides the cumulative value from the adder 167by the sum ΣCi of the interpolation coefficients from the adder 167 tooutput the result of division to the register (R4) 170, which thenoutputs the result of division from the divider 169, that is aninterpolated value X of the point of interpolation x, in synchronismwith an EN signal every four clock periods, here the number 13 timing.

According to the present embodiment, as described above, the HD formatpicture signals and the SD format picture signals can be interpolatedusing the same circuit, that is the interpolation circuit 22. Meanwhile,since 4-point interpolation processing is executed for the picturesignals of the HD format, whereas the 16-point interpolation processinginstead of the 4-point interpolation processing is executed for the SDformat picture signals, the interpolated value obtained may be of thequality equivalent to that of the conventional equipment dedicated to SDformat. It should be noted that the present invention may be applied toall sorts of the equipment configured for processing picture signals.

Although the above-described sequence of operations can be performed ona hardware, it may also be executed by the software. If the sequence ofoperations is to be executed on the software, the program forming thesoftware is installed in a dedicated hardware built in a computer.Alternatively, the program forming the software is installed from arecording medium in e.g., a general-purpose personal computer capable ofexecuting various functions.

The recording medium is formed not only by package media, such as amagnetic disc 6, inclusive of a floppy disc, an optical disc 7,inclusive of a CD-ROM (Compact Disc-Read-Only memory) and DVD (DigitalVersatile Disc), a magneto-optical disc 8, inclusive of MD (Mini-Disc),or a semiconductor memory 9, having the program pre-recorded thereon,but also by a ROM or a hard disc, having the program pre-recordedthereon and which is furnished to the user as it is built in thecomputer from the outset. In the present specification, the stepsstating the program recorded on the recording medium includes parallelprocessing or batch-wise processing, in addition to the processingexecuted chronologically in an explicitly stated sequence. Meanwhile,the system herein means an entire apparatus comprised of pluralcomponent units.

INDUSTRIAL APPLICABILITY

In the picture processing method and apparatus and a program for arecording medium, according to the present invention, input picturesignals are stored in a memory, the picture signals recorded on thememory are read out simultaneously every preset number of picturesignals, and the plural picture signals, recorded in the memory, areprocessed in a preset manner to interpolate picture signals at a presetposition. Since the operating frequency as well as the number of timesof operations of the readout processing and the interpolation processingis controlled in keeping with the format of the input picture signals,4-point interpolation processing and the 16-point interpolationprocessing can be executed for the picture signals of the HD format andfor the picture signals of the SD format, respectively.

Moreover, in the picture processing method and apparatus and the programfor the recording medium according to the present invention, inputpicture signals are stored in a memory, an imaginary area is set arounda picture formed from the picture signals, and picture signals aregenerated for the imaginary area and the so generated picture signalsfor the imaginary area are stored in the memory, so that the sameinterpolation processing can be applied irrespective of the positionsfor interpolation.

In the picture processing method and apparatus and the program for therecording medium according to the present invention, in which chromasignals for a preset position are interpolated, using plural separatedconsecutive chroma signals, and in which the so interpolated chromasignals are output simultaneously with the associated luminance signals,it becomes possible to utilize the memory efficiently or to carry outprocessing for color adjustment.

In the picture processing method and apparatus and the program for therecording medium according to the present invention, in which picturesignals input in the horizontal scanning sequence are alternatelywritten, in terms of a preset quantity as a unit, in a plural number ofbanks of a first information recording medium, the picture signals areread out alternately from the different banks of the first informationrecording medium, in terms of a preset quantity as a unit, and picturesignals are output, in terms of a preset quantity as a unit, in the samesequence as the writing sequence, it becomes possible to change thescanning direction using a recording medium as the first informationrecording medium featuring burst information transfer.

Moreover, in the picture processing method and apparatus and the programfor the recording medium according to the present invention, in whichthe bit width of the picture signals is converted as the bit width ofthe chroma signals of the input picture signals is diminished, itbecomes possible to use a 36-bit general-purpose memory to reduce thecost.

1. A picture processing apparatus for processing picture signals ofdifferent formats that include a first format and a second format,comprising: ex-area adding means for adding ex-areas around the areaindicated by the input picture signals; storage means for storing inputpicture signals in a memory; read-out means for simultaneously readingout said picture signals stored in said memory in terms of a presetnumber of the picture signals as a unit; interpolation means forinterpolating picture signals for a preset position by executing presetcalculations on the plural picture signals read out by said readoutmeans from said memory; and control means for controlling the operatingfrequency and the number of times of operations of said readout meansand said interpolation means in keeping with the formats of the inputpicture signals, wherein a 4-point interpolation processing is executedfor the picture signals of a high-definition (“HD”) format and a16-point interpolation processing is executed for the picture signals ofa standard definition (“SD”) format, respectively, wherein a number ofpixels of the ex-areas are determined by a number of pixels used by theinterpolation means, wherein the interpolation means implements aninterpolating process independent of a location of the preset position,and wherein the added ex-area adds one or more dummy pixels adjacent toan edge pixel so that when the preset position is at an edge of the areadefined by the picture signals, the interpolation means implements thesame interpolation process, the one or more dummy pixels being disposedoutside the area defined by the picture pixels and generating a blackarea.
 2. The picture processing apparatus according to claim 1 wherein,when the picture signals of the first format are input, said controlmeans changes said operating frequency and the number of times ofoperations to values as large as four times those when the picturesignals of the second format are input.
 3. The picture processingapparatus according to claim 2 further comprising: conversion means forapplying field/frame conversion to picture signals of the first formatand for doubling the number of pixels in the vertical direction.
 4. Thepicture processing apparatus according to claim 2 wherein said firstformat is an SD format and wherein said second format is an HD format.5. The picture processing apparatus according to claim 1 wherein, whenthe picture signals of the first format are input, said interpolationmeans perform preset calculations on 16 of said picture signals tointerpolate picture signals for a preset position, under control fromsaid control means, and wherein, when the picture signals of the secondformat are input, said interpolation means perform preset calculationson 4 of said picture signals to interpolate picture signals for a presetposition, under control from said control means.
 6. A picture processingmethod for processing picture signals of different formats that includea first format and a second format, comprising: an ex-area adding stepof adding ex-areas around the area indicated by the input picturesignals; a storage step of storing input picture signals in a memory; aread-out step of simultaneously reading out said picture signals storedin said memory in terms of a preset number of the picture signals as aunit; an interpolation step of interpolating picture signals for apreset position by executing preset calculations on the plural picturesignals read out in said readout step from said memory; and a controlstep of controlling the operating frequency and the number of times ofoperations of said readout step and said interpolation step in keepingwith the formats of the input picture signals, wherein a 4-pointinterpolation processing is executed for the picture signals of ahigh-definition (“HD”) format and a 16-point interpolation processing isexecuted for the picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation step, wherein theinterpolation step implements an interpolating process independent of alocation of the preset position, and wherein the added ex-area adds oneor more dummy pixels adjacent to an edge pixel so that when the presetposition is at an edge of the area defined by the picture signals, theinterpolation step implements the same interpolation process, the one ormore dummy pixels being disposed outside the area defined by the picturepixels and generating a black area.
 7. A non-transitory recording mediumincluding a computer-readable program for picture processing, recordedthereon, said program processing picture signals of different formatsthat include a first format and a second format; said programcomprising: an ex-area adding step of adding ex-areas around the areaindicated by the input picture signals; a storage step of storing inputpicture signals in a memory; a read-out step of simultaneously readingout said picture signals stored in said memory in terms of a presetnumber of the picture signals as a unit; an interpolation step ofinterpolating picture signals for a preset position by executing presetcalculations on the plural picture signals read out in said readout stepfrom said memory; and a control step of controlling the operatingfrequency and the number of times of operations of said readout step andsaid interpolation step in keeping with the formats of the input picturesignals, wherein a 4-point interpolation processing is executed for thepicture signals of a high-definition (“HD”) format and a 16-pointinterpolation processing is executed for the picture signals of astandard definition (“SD”) format, respectively, wherein a number ofpixels of the ex-areas are determined by a number of pixels used by theinterpolation step, wherein the interpolation step implements aninterpolating process independent of a location of the preset position,and wherein the added ex-area adds one or more dummy pixels adjacent toan edge pixel so that when the preset position is at an edge of the areadefined by the picture signals, the interpolation step implements thesame interpolation process, the one or more dummy pixels being disposedoutside the area defined by the picture pixels and generating a blackarea.
 8. A picture processing apparatus for interpolating picturesignals, comprising: storage means for storing said picture signalscorresponding to input pixels in a memory; generating means for settingan imaginary area around a picture formed by said picture signals forgenerating said picture signals associated with said imaginary area;storage means for storing said picture signals associated with saidimaginary area, generated by said generating means; readout means forreading out said plural picture signals associated with plural pixelslying in the vicinity of a preset position; and interpolation means forinterpolating said picture signals associated with said preset positionusing plural picture signals associated with said plural pixels read outby said readout means, wherein a 4-point interpolation processing isexecuted for the picture signals of a high-definition (“HD”) format anda 16-point interpolation processing is executed for the picture signalsof a standard definition (“SD”) format, respectively, wherein a numberof pixels of the imaginary area are determined by a number of pixelsused by the interpolation means, wherein the interpolation meansimplements an interpolating process independent of a location of thepreset position, and wherein the imaginary area adds one or more dummypixels adjacent to an edge pixel so that when the preset position is atan edge of the area defined by the picture signals, the interpolationmeans implements the same interpolation process, the one or more dummypixels being disposed outside the area defined by the picture pixels andgenerating a black area.
 9. The picture processing apparatus accordingto claim 8 wherein said readout means reads out four of said picturesignals associated with four of said pixels lying on the upper and lowersides and on the left and right sides of said preset position; saidinterpolation means interpolating said picture signals associated withsaid preset position using the four picture signals read out by saidreadout means.
 10. A picture processing method for interpolating picturesignals, comprising: a storage step of storing said picture signalscorresponding to input pixels in a memory; a generating step of settingan imaginary area around a picture formed by said picture signals forgenerating said picture signals associated with said imaginary area; astorage step of storing said picture signals associated with saidimaginary area, generated by said generating step; a readout step ofreading out said plural picture signals associated with plural pixelslying in the vicinity of a preset position; and an interpolation step ofinterpolating said picture signals associated with said preset positionusing plural picture signals associated with said plural pixels read outby said readout step, wherein a 4-point interpolation processing isexecuted for the picture signals of a high-definition (“HD”) format anda 16-point interpolation processing is executed for the picture signalsof a standard definition (“SD”) format, respectively, wherein a numberof pixels of the imaginary area are determined by a number of pixelsused by the interpolation step, wherein the interpolation stepimplements an interpolating process independent of a location of thepreset position, and wherein the imaginary area adds one or more dummypixels adjacent to an edge pixel so that when the preset position is atan edge of the area defined by the picture signals, the interpolationstep implements the same interpolation process, the one or more dummypixels being disposed outside the area defined by the picture pixels andgenerating a black area.
 11. A non-transitory recording medium includinga computer-readable program for picture processing, recorded thereon,said program interpolating picture signals; said program comprising: astorage step of storing said picture signals corresponding to inputpixels in a memory; a generating step of setting an imaginary areaaround a picture formed by said picture signals for generating saidpicture signals associated with said imaginary area; a storage step ofstoring said picture signals associated with said imaginary area,generated by said generating step; a readout step of reading out saidplural picture signals associated with plural pixels lying in thevicinity of a preset position; and an interpolation step ofinterpolating said picture signals associated with said preset positionusing plural picture signals associated with said plural pixels read outby said readout step, wherein a 4-point interpolation processing isexecuted for the picture signals of a high-definition (“HD”) format anda 16-point interpolation processing is executed for the picture signalsof a standard definition (“SD”) format, respectively, wherein a numberof pixels of the imaginary area are determined by a number of pixelsused by the interpolation step, wherein the interpolation stepimplements an interpolating process independent of a location of thepreset position, and wherein the imaginary area adds one or more dummypixels adjacent to an edge pixel so that when the preset position is atan edge of the area defined by the picture signals, the interpolationstep implements the same interpolation process, the one or more dummypixels being disposed outside the area defined by the picture pixels andgenerating a black area.
 12. A picture processing apparatus forinterpolating picture signals including at least luminance signals andchroma signals, comprising: ex-area adding means for adding ex-areasaround the area indicated by the input picture signals; separating meansfor separating said chroma signals from said picture signalscorresponding to sequentially input pixels; interpolation means forinterpolating chroma signals associated with a preset position using aplurality of consecutive chroma signals, as separated by said separatingmeans; and outputting means for outputting said chroma signals,interpolated by said interpolation means, simultaneously withcorresponding luminance signals, wherein a 4-point interpolationprocessing is executed for the picture signals of a high-definition(“HD”) format and a 16-point interpolation processing is executed forthe picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation means, wherein theinterpolation means implements an interpolating process independent of alocation of the preset position, and wherein the added ex-area adds oneor more dummy pixels adjacent to an edge pixel so that when the presetposition is at an edge of the area defined by the picture signals, theinterpolation means implements the same interpolation process, the oneor more dummy pixels being disposed outside the area defined by thepicture pixels and generating a black area.
 13. The picture processingapparatus according to claim 12 wherein said picture signals are 4:2:2picture signals comprised of luminance signals Y, chroma signals U andchroma signals V.
 14. The picture processing apparatus according toclaim 12 wherein said interpolation means interpolates said chromasignals associated with an intermediate position of second and thirdchroma signals using four of said chroma signals separated by saidseparating means.
 15. The picture processing apparatus according toclaim 12 wherein said picture signals associated with said pixels areinput in the horizontal scanning sequence.
 16. The picture processingapparatus according to claim 12 further comprising: removing means forremoving high frequency components of said picture signals associatedwith said sequentially input pixels.
 17. A picture processing method forinterpolating picture signals including at least luminance signals andchroma signals, comprising: an ex-area adding step of adding ex-areasaround the area indicated by the input picture signals; a separatingstep of separating said chroma signals from said picture signalscorresponding to sequentially input pixels; an interpolation step ofinterpolating chroma signals associated with a preset position using aplurality of consecutive chroma signals, as separated by said separatingstep; and an outputting step of outputting said chroma signals,interpolated by said interpolation step, simultaneously withcorresponding luminance signals, wherein a 4-point interpolationprocessing is executed for the picture signals of a high-definition(“HD”) format and a 16-point interpolation processing is executed forthe picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation step, wherein theinterpolation step implements an interpolating process independent of alocation of the preset position, and wherein the imaginary area adds oneor more dummy pixels adjacent to an edge pixel so that when the presetposition is at an edge of the area defined by the picture signals, theinterpolation step implements the same interpolation process, the one ormore dummy pixels being disposed outside the area defined by the picturepixels and generating a black area.
 18. A non-transitory recordingmedium including a computer-readable program for picture processing,recorded thereon, said program interpolating picture signals at leastincluding luminance signals and chroma signals; said program comprising:an ex-area adding step of adding ex-areas around the area indicated bythe input picture signals; a separating step of separating said chromasignals from said picture signals corresponding to sequentially inputpixels; an interpolation step of interpolating chroma signals associatedwith a preset position using a plurality of consecutive chroma signals,as separated by said separating step; and an outputting step ofoutputting said chroma signals, interpolated by said interpolation step,simultaneously with corresponding luminance signals, wherein a 4-pointinterpolation processing is executed for the picture signals of ahigh-definition (“HD”) format and a 16-point interpolation processing isexecuted for the picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation step, wherein theinterpolation step implements an interpolating process independent of alocation of the preset position, and wherein the imaginary area adds oneor more dummy pixels adjacent to an edge pixel so that when the presetposition is at an edge of the area defined by the picture signals, theinterpolation step implements the same interpolation process, the one ormore dummy pixels being disposed outside the area defined by the picturepixels and generating a black area.
 19. A picture processing apparatusfor changing the scanning direction for picture signals, comprising:ex-area adding means for adding ex-areas around the area indicated bythe input picture signals; writing means for alternately writing saidpicture signals, input in the horizontal scanning sequence, in differentones of a plurality of banks of a first information recording medium,from one preset unit volume to another; readout/writing means foralternately reading out said picture signals every preset unit volume,for writing the information signals in a second information recordingmedium; and output control means for outputting said picture signalsevery preset unit volume from said second information recording mediumin accordance with the writing sequence, wherein a 4-point interpolationprocessing is executed for the picture signals of a high-definition(“HD”) format and a 16-point interpolation processing is executed forthe picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation processing, wherein theinterpolating processing is implemented independent of a location of thepreset position, and wherein the imaginary area adds one or more dummypixels adjacent to an edge pixel so that when the preset position is atan edge of the area defined by the picture signals, the interpolationmeans implements the same interpolation process, the one or more dummypixels being disposed outside the area defined by the picture pixels andgenerating a black area.
 20. The picture processing apparatus accordingto claim 19 wherein said first information recording medium is an SDRAM.21. The picture processing apparatus according to claim 19 wherein saidsecond information recording medium is an SRAM.
 22. A picture processingmethod for changing the scanning direction for picture signals,comprising: an ex-area adding step of adding ex-areas around the areaindicated by the input picture signals; a writing step of alternatelywriting said picture signals, input in the horizontal scanning sequence,in different ones of a plurality of banks of a first informationrecording medium, from one preset unit volume of said picture signals toanother; a readout/writing step of alternately reading out said picturesignals every preset unit volume of said picture signals, for writingthe information signals in a second information recording medium; and anoutput control step of outputting said picture signals every preset unitvolume of said picture signals from said second information recordingmedium in accordance with the writing sequence, wherein a 4-pointinterpolation processing is executed for the picture signals of ahigh-definition (“HD”) format and a 16-point interpolation processing isexecuted for the picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation processing, wherein theinterpolating processing is implemented independent of a location of thepreset position, and wherein the imaginary area adds one or more dummypixels adjacent to an edge pixel so that when the preset position is atan edge of the area defined by the picture signals, the interpolationstep implements the same interpolation process, the one or more dummypixels being disposed outside the area defined by the picture pixels andgenerating a black area.
 23. A non-transitory recording medium includinga computer-readable program for picture processing, recorded thereon,said program causing the scanning direction of picture signals to bechanged; said program comprising: an ex-area adding step of addingex-areas around the area indicated by the input picture signals; awriting step of alternately writing said picture signals, input in thehorizontal scanning sequence, in different ones of a plurality of banksof a first information recording medium, from one preset unit volume ofsaid picture signals to another; a readout/writing step of alternatelyreading out said picture signals every preset unit volume of said inputpicture signals, for writing the information signals in a secondinformation recording medium; and an output control step of outputtingsaid picture signals every preset unit volume of said input picturesignals from said second information recording medium in accordance withthe writing sequence, wherein a 4-point interpolation processing isexecuted for the picture signals of a high-definition (“HD”) format anda 16-point interpolation processing is executed for the picture signalsof a standard definition (“SD”) format, respectively, wherein a numberof pixels of the ex-areas are determined by a number of pixels used bythe interpolation processing, wherein the interpolating processing isimplemented independent of a location of the preset position, andwherein the imaginary area adds one or more dummy pixels adjacent to anedge pixel so that when the preset position is at an edge of the areadefined by the picture signals, the interpolation step implements thesame interpolation process, the one or more dummy pixels being disposedoutside the area defined by the picture pixels and generating a blackarea.
 24. A picture processing apparatus for changing a bit width ofpicture signals, comprising: ex-area adding means for adding ex-areasaround the area indicated by the input picture signals; conversion meansfor reducing the bit width of chroma signals of input picture signals tochange the bit width of said picture signals; storage means for storingsaid picture signals, converted in bit width by said conversion means toa preset bit width, in a memory, wherein said conversion means diminishthe bit width of said chroma signals of the input picture signals of40-bit width to picture signals of 36 bit width; and interpolation meansfor interpolating picture signals for a preset position by executingpreset calculations on said picture signals read out by a readout meansfrom said memory, wherein a 4-point interpolation processing is executedfor the picture signals of a high-definition (“HD”) format and a16-point interpolation processing is executed for the picture signals ofa standard definition (“SD”) format, respectively, wherein a number ofpixels of the ex-areas are determined by a number of pixels used by theinterpolation means wherein the interpolating processing meansimplements an interpolation processing independent of a location of thepreset position, and wherein the imaginary area adds one or more dummypixels adjacent to an edge pixel so that when the preset position is atan edge of the area defined by the picture signals, the interpolationmeans implements the same interpolation process, the one or more dummypixels being disposed outside the area defined by the picture pixels andgenerating a black area.
 25. The picture processing apparatus accordingto claim 24 wherein said memory is an SRAM of a 36 bit width.
 26. Thepicture processing apparatus according to claim 24, wherein the inputpicture signals are picture signals of a 40-bit width comprised of10-bit luminance signals Y, 10-bit chroma signals U, 10-bit chromasignals V and 10-bit key signals K.
 27. A picture processing method forchanging a bit width of picture signals, comprising: an ex-area addingstep of adding ex-areas around the area indicated by the input picturesignals; a conversion step of reducing the bit width of chroma signalsof input picture signals to change the bit width of said picturesignals; a storage step of storing said picture signals, converted inbit width in said conversion step to a preset bit width, in a memory,wherein said conversion means diminish the bit width of said chromasignals of the input picture signals of 40-bit width to picture signalsof 36 bit width; and an interpolation step for interpolating picturesignals for a preset position by executing preset calculations on saidpicture signals read out from said memory, wherein a 4-pointinterpolation processing is executed for the picture signals of ahigh-definition (“HD”) format and a 16-point interpolation processing isexecuted for the picture signals of a standard definition (“SD”) format,respectively, wherein a number of pixels of the ex-areas are determinedby a number of pixels used by the interpolation step, wherein theinterpolating processing step implements an interpolation processingindependent of a location of the preset position, and wherein theimaginary area adds one or more dummy pixels adjacent to an edge pixelso that when the preset position is at an edge of the area defined bythe picture signals, the interpolation step implements the sameinterpolation process, the one or more dummy pixels being disposedoutside the area defined by the picture pixels and generating a blackarea.
 28. A non-transitory recording medium including acomputer-readable program for picture processing, recorded thereon, saidprogram causing a bit width of picture signals to be changed; saidprogram comprising: an ex-area adding step of adding ex-areas around thearea indicated by the input picture signals; a conversion step ofreducing the bit width of chroma signals of input picture signals tochange the bit width of said picture signals; a storage step of storingsaid picture signals, converted in bit width in said conversion step toa preset bit width, in a memory, wherein said conversion means diminishthe bit width of said chroma signals of the input picture signals of40-bit width to picture signals of 36 bit width; and interpolation meansfor interpolating picture signals for a preset position by executingpreset calculations on said picture signals read out by a readout meansfrom said memory, wherein a 4-point interpolation processing is executedfor the picture signals of a high-definition (“HD”) format and a16-point interpolation processing is executed for the picture signals ofa standard definition (“SD”) format, respectively, wherein a number ofpixels of the ex-areas are determined by a number of pixels used by theinterpolation step, wherein the interpolating processing step implementsan interpolation processing independent of a location of the presetposition, and wherein the imaginary area adds one or more dummy pixelsadjacent to an edge pixel so that when the preset position is at an edgeof the area defined by the picture signals, the interpolation stepimplements the same interpolation process, the one or more dummy pixelsbeing disposed outside the area defined by the picture pixels andgenerating a black area.